The present invention relates generally to digital interface circuitry and, more particularly, to a technique for voltage level shifting in input circuitry.
As digital circuitry and systems have evolved, they have been designed to utilize steadily lower supply voltage levels. For example, early Transistor-Transistor-Logic (TTL) digital logic circuits typically operated from a 5 volt (V) power supply. As the need for power efficiency has grown, primarily with respect to mobile devices, the typical power supply voltage for devices dropped to 3V, and now devices designed to operate from 1.8V supply levels dominate the market. Also, as the transistor geometries for integrated circuit technology have dropped, some devices are unable to operate using higher voltage supply levels. Further, lower voltage levels reduce output voltage swings and, consequently, the noise produced circuits.
However, many architectural standards, such as bus standards, were developed when a different logical voltage level was the norm. Also, systems may incorporate devices having different supply voltage requirements. For example, a system may include a processor, memory controller, and memory that are designed to operate using 1.8V, while the system bus may be designed to operate using 3.3V. To alleviate this problem, some systems are designed to support several different voltage levels. For example, the Peripheral Control Interface (PCI) local bus is designed to operate using both 5V and 3.3V signaling levels. See the PCI Local Bus Specification version 2.2, which is hereby incorporated by reference herein in its entirety.
FIG. 1 illustrates an example of a system architecture 10 utilizing a PCI local bus 40. A microprocessor 20 directly interfaces to a cache 22 and memory controller 30 via a processor bus 24. Memory controller 30 also interfaces to a dynamic random access memory (DRAM) device 32 and to PCI local bus 40. The memory controller 30 provides a bridge to the PCI bus from the processor bus 24 and handles access to DRAM 32 and to devices coupled to PCI local bus 40 for the processor 20. System architecture 10 includes a representative selection of peripheral devices such as, for example, a network interface 42 for communications with an external network such as a local area network (LAN), a graphics interface 44 for driving a video output, a peripheral interface 46 for interfacing to other peripheral devices, such as keyboards, modems, etc., and a disk controller 50 for controlling bulk storage to disk 52.
Today, processor 20, cache 22, memory controller 30, and DRAM 32 are often designed for use with a 1.8V supply. However, as noted above, the PCI standard currently calls for logic signaling levels based on 3.3V or 5V. This raises the problem of interfacing between devices operating using different supply levels.
Systems may incorporate devices operating from a variety of supply sources having different levels. FIG. 2 is a diagram of a Rambus clock generation architecture 60, wherein a system clock source 80 operating from voltage supply VDDIR (e.g., 3V) produces a reference clock signal REFCLK that is input to a Direct Rambus Clock Generator (DRCG) circuit 70. The DRCG circuit 70 is operating from another voltage supply VDD (e.g., 1.8V) and producing a bus clock signal BUS CLOCK, which is based on a Rambus Signal Level (RSL) using supply voltage VDDIPD (e.g., 1.8V), which results in a signal voltage swing between 1.0V and 1.8V. The bus clock signal BUS CLOCK, in turn, drives Rambus DRAMs (RDRAMs) 92-94, which are controlled by memory controller 90 through the use of a termination resistor 62. See Direct Rambus Clock Generator, Document DL-0056, Version 1.2, Rambus Inc., November 2000, which is hereby incorporated by reference herein in its entirety.
In order to deal with voltage differences between external signal levels (e.g., the bus clock signal BUS CLOCK operating between 1.0V and 1.8V) and internal voltage levels (e.g., the memory controller 90 typically operating below 1.8V), an input level shifter stage is typically used. FIG. 3 illustrates one example of an input level shifter circuit relating to the clock generation architecture 60 of FIG. 2. An output pin of clock source 80 includes an output driver 82 that operates from the supply voltage VDDIR, which typically ranges from 1.3V to 3.3V. The output signal from output driver 82 reflects the voltage level of VDDIR. The output driver 82 drives an input pin of DRCG circuit 70, which includes an input comparator 72 that operates from supply voltage VDDIPD. DRCG circuit 70 also has an input that receives VDDIR, which is divided by resistors 74 and 76 to obtain a threshold voltage that is input to comparator 72. Comparator 72 compares the voltage signal received from output driver 82 with the threshold voltage obtained by dividing VDDIR in order to generate a received signal having logic voltage levels that reflect the voltage level VDDIPD.
Conventional input level shifters appear in a variety of forms, such as an operational amplifier network, a resistive divider network, or a source follower. FIG. 3 illustrates an example of a combination resistive divider and operational amplifier, where comparator 72 is implemented as an operational amplifier. FIG. 4 illustrates an example of a source follower input circuit 100 comprising a transistor 102, an input resistor 104, and a source resistor 106. In source follower circuit 100, a higher voltage signal received at DIN is reflected at the source of transistor 102, which is coupled to Dout, while the drain of transistor 102 is coupled to a supply voltage VDDI. The magnitude of the voltage being shifted in source follower circuit 100 is determined by the threshold voltage of transistor 102.
A variety of other conventional level shifter circuits are shown in U.S. Pat. Nos. 6,160,421; 6,097,215; 5,986,472; 5,973,508; 5,867,010; 5,757,712, 5,751,168; 5,663,663; 5,534,798; and 5,534,795, all of which are hereby incorporated by reference herein in their entirety.
Conventional level shifters have a limited ability to shift from an external voltage level to an internal voltage level. Source follower circuits are dependent on the transistor threshold voltage Vt and tolerate only a narrow range between the external voltage level and the internal supply voltage. Consequently, source follower circuits must be tuned to each particular application and technology, and in general will affect the yield of silicon (product). In addition, source follower circuits do not provide gain for input signals. In resistive divider circuits, the ratio of the resistors must be selected for the relationship between the external and internal voltage sources for the particular application and technology and, as a result, cannot tolerate much variation in the external supply voltage. Also, the introduction of resistance to the receive path will slow the response of the circuit making resistive dividers unsuitable for high speed applications.
Operational amplifier based circuits can be configured to introduce gain to the input signal path. However, the gain of the operational amplifier is determined by the ratio of the feedback resistance to the input resistance for the amplifier. This ratio is fixed and must be designed for a specific ratio of external to internal voltage levels. The resistance also tends to slow the circuit, resulting in poor high speed performance. For a differential input amplifier circuit, since transistors must generally be stacked and use a low internal voltage supply level (e.g., VDD less than 2Vt), the differential pair of the amplifier will typically run out of headroom to operate. In other words, the supply voltage level typically becomes insufficient to accommodate the output swing of the circuit without introducing distortion. For a single-ended input amplifier circuit, the gain offset can become quite large because the current source for the circuit may be pushed into its linear operating region. This causes distortion of the output signal for the receiver, such as duty cycle error. This occurs because there is a higher gain level when the data signal is higher, but a lower gain level when the reference voltage for the circuit is higher, since the reference voltage is less than the peak amplitude of the data.
FIG. 5 is a waveform diagram illustrating an example of the distortion that can occur due to a lack of operating headroom in a conventional receiver that utilizes a source follower to perform level shifting. In FIG. 5, waveform 110 represents a reference voltage for an input data signal represented by waveform 112. In this example, reference voltage 110 is approximately 1.4V and data signal 112 varies from 1.0V to 1.8V, which represents an RSL signal level. Likewise, waveform 114 represents a level shifted reference voltage for a level shifted data signal 116 that results from the level shifting of data signal 112. Waveform 120 represents the output voltage waveform of a gain stage that results from the input data signal 112 after it has been level shifted and amplified in a circuit having inadequate headroom.
Waveform 120 exhibits distortion due to voltage undershoot (illustrated at 122) and a flattening of the waveform (illustrated at 124) due to lack of headroom in the circuit. These occur because the performance of a traditional level shifter (e.g., a source follower) depends on the threshold levels of transistors. When designers do not have control over process and technology, a traditional level shifter tends to either level shift too much or not enough. If it shifts too much, the next stage (e.g., a gain stage) will not have enough headroom. On the other hand, if it does not shift enough, there is a gate stress problem for the following stage.
Thus, a need remains for an input circuit that operates at low supply voltage levels and is capable of level shifting higher voltage input signals with minimal distortion.
According to the present invention, a technique for voltage level shifting in input circuitry is provided. In one exemplary embodiment, the technique may be realized as a pseudo folded cascode level shifting circuit. The pseudo folded cascode level shifting circuit may comprise a differential amplifier having first and second input terminals, first and second current sinking terminals, and first and second current sourcing terminals, wherein the first and second input terminals may receive first and second input signals, respectively. The pseudo folded cascode level shifting circuit may also comprise a first current source having a control terminal for receiving a first bias control signal, and a current sinking terminal coupled to the first and second current sourcing terminals of the differential amplifier. The pseudo folded cascode level shifting circuit may further comprise a second current source having a control terminal for receiving a second bias control signal, a current sinking terminal coupled to a power supply, and a current sourcing terminal coupled to the first current sinking terminal of the differential amplifier. The pseudo folded cascode level shifting circuit may additionally comprise a third current source having a control terminal for receiving the second bias control signal, a current sinking terminal coupled to the power supply, and a current sourcing terminal coupled to the second current sinking terminal of the differential amplifier. The pseudo folded cascode level shifting circuit may still further comprise a first transistor having a control terminal for receiving a third bias control signal, a current sinking terminal coupled to the current sourcing terminal of the second current source and to the first current sinking terminal of the differential amplifier, and a current sourcing terminal. The pseudo folded cascode level shifting circuit may still additionally comprise a second transistor having a control terminal for receiving the third bias control signal, a current sinking terminal coupled to the current sourcing terminal of the third current source and to the second current sinking terminal of the differential amplifier, and a current sourcing terminal. The pseudo folded cascode level shifting circuit may even further comprise a first load coupled to the current sourcing terminal of the first transistor, and a second load coupled to the current sourcing terminal of the second transistor.
In another exemplary embodiment, the technique may be realized as a method for voltage level shifting input signals. This method may comprise receiving first and second input signals having first and second voltage levels, respectively, and then differentially amplifying the first and second input signals so as to generate first and second amplified voltage signals having first and second amplified voltage levels, respectively, wherein the first and second amplified voltage signals are substantially complementary. This method may then comprise reducing the first and second amplified voltage levels of the first and second amplified voltage signals so as to generate first and second level shifted amplified voltage signals having first and second level shifted amplified voltage levels, respectively.
In yet another exemplary embodiment, the technique may be realized as another method for voltage level shifting input signals. This method may comprise receiving first and second input voltage signals having first and second input voltage levels, respectively, wherein the first and second input voltage signals are substantially complementary. This method may then comprise converting the first and second input voltage signals into first and second current signals having first and second current levels, respectively, wherein the first and second current signals are substantially complementary. This method may then comprise converting the first and second current signals into first and second output voltage signals having first and second output voltage levels, respectively, wherein the first and second output voltage signals are substantially complementary and the first and second output voltage levels are lower than the first and second input voltage levels, respectively.
The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.